---------------------------------------------------------------------------------- -- Company: -- Engineer: T. Nakagawa -- -- Create Date: 22:41:33 02/18/2009 -- Design Name: -- Module Name: dice - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity dice is Port ( SW1 : in STD_LOGIC; SW2 : in STD_LOGIC; CLK : in STD_LOGIC; BZ : out STD_LOGIC; A1 : out STD_LOGIC; B1 : out STD_LOGIC; C1 : out STD_LOGIC; D1 : out STD_LOGIC; E1 : out STD_LOGIC; F1 : out STD_LOGIC; G1 : out STD_LOGIC; DP1 : out STD_LOGIC; A2 : out STD_LOGIC; B2 : out STD_LOGIC; C2 : out STD_LOGIC; D2 : out STD_LOGIC; E2 : out STD_LOGIC; F2 : out STD_LOGIC; G2 : out STD_LOGIC; DP2 : out STD_LOGIC); end dice; architecture Behavioral of dice is signal RUN : STD_LOGIC; signal BEEP : STD_LOGIC; signal DIGIT : STD_LOGIC_VECTOR(0 to 7); signal RLT : STD_LOGIC_VECTOR(0 to 5); signal Q : STD_LOGIC_VECTOR(17 downto 0); signal CE : STD_LOGIC; signal CNT : STD_LOGIC_VECTOR(2 downto 0); begin RUN <= not SW1; BEEP <= not SW2; process (CLK) begin if (CLK'event and CLK='1') then Q <= Q + '1'; end if; end process; process (Q) begin if (Q = "111111111111111111") then CE <= '1'; else CE <= '0'; end if; end process; process (CE) begin if (CE'event and CE = '1' and RUN = '1') then if (CNT = "101") then CNT <= "000"; else CNT <= CNT + '1'; end if; end if; end process; process (CNT) begin case CNT is when "000" => DIGIT <= "01100000"; RLT <= "100000"; when "001" => DIGIT <= "11011010"; RLT <= "010000"; when "010" => DIGIT <= "11110010"; RLT <= "001000"; when "011" => DIGIT <= "01100110"; RLT <= "000100"; when "100" => DIGIT <= "10110110"; RLT <= "000010"; when "101" => DIGIT <= "10111110"; RLT <= "000001"; when others => DIGIT <= "--------"; RLT <= "------"; end case; end process; BZ <= BEEP; A1 <= DIGIT(0); B1 <= DIGIT(1); C1 <= DIGIT(2); D1 <= DIGIT(3); E1 <= DIGIT(4); F1 <= DIGIT(5); G1 <= DIGIT(6); DP1 <= DIGIT(7); A2 <= RLT(0); B2 <= RLT(1); C2 <= RLT(2); D2 <= RLT(3); E2 <= RLT(4); F2 <= RLT(5); G2 <= '0'; DP2 <= BEEP; end Behavioral;